Amd64 处理器识别程序

olo_skyking

在这里潜水很久了，学到了不少的东西，谢谢大家！
这是我写的一个识别 Amd64 cpu的程序amd64Info。



我的开发环境：
AMD Athlon 64 3000+
OS: fedora 2 for x86_64
gcc 3.3.3

如有转载，注明出处。

olo_skyking

程序还有不足：不支持多u，只支持amd的x86_64

处理器中的TLB的相关属性对系统的页调度效率有很大影响，
我们应该探讨和考虑，将来来完成自己的操作系统。

不要因为走的远了，而忘记了KISS(Keep it simple,stupid)。
不要让我们的系统穿上厚重的盔甲，龟行。

欢迎大家讨论！

olo_skyking

这个是我的u
AMD64 CPU information

Largest Standard Function Number :       1
Processor Vendor : AuthenticAMD
Processor name   : AMD Athlon(tm) 64 Processor 3000+
Extended Family  :   0
Extended Model   :   0
Base Family      :  15
Base Model       :  12
Stepping         :   0
8Bit Brand Id    :   0
CLFLUSH size     :  64
Local APIC id    :   0
Timestamp counter:   1
Logical processor count :   0
SSE extensions support :                            yes
MMX instructions support :                          yes
SSE2 extensions support :                           yes
CMPXCHG8B instruction support :                     yes
x87 floating point unit on-chip :                   yes
Page-size extensions(4 MB pages) :                  yes
Physical-address extensions(PAE) :                  yes
CMPXCHG16B instruction support :                    no
Debugging extensions :                              yes
Virtual-mode enhancements :                         yes
Hyper-threading technology :                        no
SSE3 instruction support :                          no
SYSENTER and SYSEXIT instructions support :         yes
AMD model-specific registers(MSRs) support :        yes
Machine check exception :                           yes
Memory-type range registers:                        yes
Advanced programmable interrupt controller(APIC) :  yes
Page global extension :                             yes
Machine check architecture :                        yes
Conditional move(CMOV) instructions support :       yes
Page attributetable(PAT) :                          yes
Page-size extensions(PSE36) :                       yes
CLFLUSH instruction supported :                     yes
FXSAVE and FXRSTOR instructions support :           yes
LAHF and SAHF instruction support :                 no
Core multi-processing legacy mode support :         no
Secure virtual machine feature support :            no
LOCK MOV CR0 means MOV CR8 :                        no
SYSCALL and SYSRET instructions support :           yes
No-execute page protection support :                yes
AMD extensions to MMX instructions support :        yes
Fast FXSAVE and FXRSTOR instructions support :      no
RDTSCP instrution support :                         no
Long mode :                                         yes
3DNOWExt support :                                  yes
3DNOW support :                                     yes
Brand ID : 264
Number of cpu core : 1
Maximum linear byte address size : 40 bits
Maximum phycical byte address size : 48 bits
SVM revision : 0
Number of address space identifiers(ASID) : 0
_._._._._._._._._._._._._._._._._._._._._._._._._._._._._
Advanced Power Management Information:
Temperature sensor :                                 yes
Frequency ID control :                               yes
Voltage ID control support :                         yes
THERMTRIP support :                                  no
Software thermal control support :                   no
_._._._._._._._._._._._._._._._._._._._._._._._._._._._._
L1 cache feacture :
2MB (and 4MB) pages
        Instruction TLB number of entries : 8
        Instruction TLB associativity : Fully associative
        Data TLB number of entries : 8
        Data TLB associativity : Fully associative
4KB pages
        Instruction TLB number of entries : 32
        Instruction TLB associativity : Fully associative
        Data TLB number of entries : 32
        Data TLB associativity : Fully associative

Data cache line size : 64 Byte per line
Data cache lines per tag : 1 lines per tag
Data cache associativity : 2-way associative
Data cache size : 64 KB

Instruction cache line size : 64 Bytes per line
Instruction cache lines per tag : 1 lines per tag
Instruction cache associativity : 2-way associative
Instruction cache size : 64 KB
_._._._._._._._._._._._._._._._._._._._._._._._._._._._._
L2 cache feacture:
2MB (and 4MB) pages
        Instruction TLB number of entries : 0
        Instruction TLB associativity : The L2 cache or TLB is disabled
        Data TLB number of entries : 0
        Data TLB associativity : The L2 cache or TLB is disabled
4KB pages:
        Instruction TLB number of entries : 512
        Instruction TLB associativity : 4-way associative
        Data TLB number of entries : 512
        Data TLB associativity : 4-way associative
Cache line size: 64 Byte per line
Cache lines per tag: 1 lines per tag
Cache associativity: 16-way associative
Cache size: 512 KB
_._._._._._._._._._._._._._._._._._._._._._._._._._._._._
Test time : Mon Dec 19 15:37:01 2005