|
程序目录结构: ./main/main.c ./src/sub.c
输出: ./out/his/ ./out/main/
Makefile如下:
SOURCE_DIR := .
BINARY_DIR := ./out
modules := main src
sources := $(foreach m,$(modules),$(wildcard $(SOURCE_DIR)/$m/*.c))
objects := $(call source-to-object,$(sources))
source-dir-to-binary-dir = $(addprefix $(BINARY_DIR)/, $(patsubst $(SOURCE_DIR)/%,%,$1))
source-to-object = $(call source-dir-to-binary-dir, $(subst .c,.o,$(filter %.c,$1)))
$(program)(objects)
gcc $(CFLAGS) -o $@ $^
define one-compile-rule
$12
@gcc $(CFLAGS) -c $$< -o $$@
endef
问题来了:
---------------------------------------------------------------------------------
使用下面两行:
$(eval $(call one-compile-rule,./out/main/main.o,./main/main.c))
$(eval $(call one-compile-rule,./out/src/sub.o,./src/sub.c))
一切正常,生成.o文件(./out/his/ ./out/main/下),生成可执行程序$(program).
---------------------------------------------------------------------------------
上面两行不使用换成下面:
define compile-rules
$(foreach s,$(sources), \
$(call one-compile-rule,$(call source-to-object,$s),$s))
endef
$(eval $(call compile-rules))
make一下:
ERRORgcc: ./out/src/sub.o:./src/sub.c 没有那个文件或文件夹
怪哉怪哉,高手们指点指点,到底哪错了?万分感谢 |
|