传龙芯3可以兼容X86指令？

narcissus

This talk will give first a brief introduction to Loongson Processors.

The Loongson project is the first attempt to design high performance general-purpose microprocessors in China. The latest Loongson-2F is a 1GHz, 64-bit four-issue, out-of-order execution RISC processor that implements MIPS64 instruction set. Loongson-2F has been volume produced and used in many areas such as low-cost PC and embedded applications.

After an analyzing of technical and industrial trends of CPU, this talk will also introduces the Loongson-3 which is a multi-core processor based on the 64-bit superscalar Godson-2 CPU core. It takes a scalable CMP architecture in which processors and global addressed L2 cache modules are connected in a distributed way and coherence of multiple L1 copies of the same L2 block is maintained with a directory-based cache coherence protocol. The CPU core of Loongson-3 is enhanced to support efficient X86 to MIPS binary translation, and to optimize performance, power consumption, reliability and debug methods.

龙芯3，基于龙芯2F，64位处理器，乱序执行与RISC架构，据称是一款多核心处理器。因为2F已经支持4-issue，那么龙芯3很可能是8-16 issue，内部通过某种“解码器”实现MIPS到X86的转换

xusamuel

Post by narcissus;1868551
This talk will give first a brief introduction to Loongson Processors.

The Loongson project is the first attempt to design high performance general-purpose microprocessors in China. The latest Loongson-2F is a 1GHz, 64-bit four-issue, out-of-order execution RISC processor that implements MIPS64 instruction set. Loongson-2F has been volume produced and used in many areas such as low-cost PC and embedded applications.

After an analyzing of technical and industrial trends of CPU, this talk will also introduces the Loongson-3 which is a multi-core processor based on the 64-bit superscalar Godson-2 CPU core. It takes a scalable CMP architecture in which processors and global addressed L2 cache modules are connected in a distributed way and coherence of multiple L1 copies of the same L2 block is maintained with a directory-based cache coherence protocol. The CPU core of Loongson-3 is enhanced to support efficient X86 to MIPS binary translation, and to optimize performance, power consumption, reliability and debug methods.

龙芯3，基于龙芯2F，64位处理器，乱序执行与RISC架构，据称是一款多核心处理器。因为2F已经支持4-issue，那么龙芯3很可能是8-16 issue，内部通过某种“解码器”实现MIPS到X86的转换

binary translation?

poet

一般指令集之间动态转换的效率只有原生CPU的1/60-1/80的性能。就算龙心能把这个性能提高到 1/10 ，也是没有什么使用价值的呀。

zhong

我在等着龙芯4...........不过不知道龙芯3能出多少量...哈

cobranail

Post by poet;1878378
一般指令集之间动态转换的效率只有原生CPU的1/60-1/80的性能。就算龙心能把这个性能提高到 1/10 ，也是没有什么使用价值的呀。

这也不一定，看苹果的rosetta技术，x86上运行powerpc的程序，只是加载速度慢点，运行起来也不会慢很多

Xorcerer

微软DotNet平台，启动前把伪汇编翻译成本地汇编，还可以针对当前CPU优化，不知道芯片类的产品能否做到？

wide288

这么发展上去，走的就不是微机家用机的路线了，
是巨型机的路子了。

wide288

多核处理器，多个处理器，多片板子。